The present invention relates to techniques of fabricating a semiconductor integrated circuit (hereinafter abbreviated to IC') device and, more particularly, to techniques effectively applicable to a process of forming through holes in a layer insulating film formed on a semiconductor substrate, for connecting wiring lines formed in an upper wiring layer overlying the layer insulating film and those formed in a lower wiring layer underlying the layer insulating film.
A gate array large-scale logic integrated circuit (gate array logic LSIC chip) is one of IC devices. The gate array logic LSIC chip is provided with a logic circuit comprising a plurality of elemental cells arranged in a matrix in a central area of a plurality of a major surface of a semiconductor chip. A plurality of I/O buffers are arranged so as to surround the logic circuit. A plurality of bonding pads to be electrically connected to external devices are arranged in a peripheral region of the semiconductor chip so as to surround the arrangement of the I/O buffers and so as to correspond to the I/O buffers.
In the recent gate array logic LSIC chip of this kind, the bonding pads are arranged in two or three rows along the edges of the semiconductor chip to cope with increase in the number of the bonding pads required by increase in the size of integration of the basic cells of the logic circuit. The bonding pads on each row are displaced by half the pitch thereof relative to the bonding pads on the adjacent rows so that the bonding pads are arranged in a zigzag arrangement, whereby the effective pitch of the bonding pads is reduced and an increased number of bonding pads can be arranged on a semiconductor chip of the same size. A logic LSIC chip provided with bonding pads in a zigzag arrangement is disclosed in Japanese Patent Laid-Open No. Hei 3-173433.
If the bonding pads are arranged in a zigzag arrangement to reduce the effective pitch of the bonding pads, the pitch of wiring lines connecting the internal circuits to the bonding pads (hereinafter referred to as "connecting leads") must be reduced. Consequently, the coupling capacitance between the adjacent connecting leads increases to increase delay attributable to the connecting leads.
When the thickness of wiring lines is reduced with the miniaturization of semiconductor elements, current density in the connecting leads increases to deteriorate resistance against EMD (electromigration destruction) and to cause voltage drop due to increase in the resistance of the wiring lines. Accordingly, it is difficult to connect power lines (Vcc, GND) and signal lines which carries high currents by the connecting leads to the bonding pads.